HSINCHU, TAIWAN -- Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, today announced that its MIPI D-PHY and V-by-One (VBO) PHY IP portfolios now support processes that range from 55nm to 22nm on UMC platform. Faraday has shipped over 100 million video interface IP solutions for AIoT, industrial, consumer, and automotive applications, which includes ASIC and IP business models.

Faraday’s newly released MIPI D-PHY IP on 22nm features a low operating voltage of 0.8V, resulting in a 12% reduction in power consumption and a 10% decrease in chip area compared to its 28nm predecessor. Additionally, the solution includes multiple-TX-lanes with data rates ranging from 80Mbps to 2.5Gbps per lane for high frame rate video, offers customizable combo IO for various video RX interfaces, and provides flexible data and clock lane configurations to accommodate diverse device interfaces.

Faraday’s V-by-One HS PHY IP on 22nm complies with V-by-One HS V1.4/1.5 standards for transmitter and receiver and supports data rates from 600Mbps to 4Gbps per lane. It reduces power consumption by 20% while operating at 0.8V and decreases chip area by 30% compared to its 28nm predecessor. In addition, the PHY IP supports scrambling and clock data recovery (CDR), effectively addressing the skew issue and reducing EMI.

“Faraday continues to invest in high-speed video interface IP solutions, offering application-oriented design service that include IP customization for multiple-lane configuration and combo IO solution, as well as seamless porting to other fabrication processes,” said Flash Lin, COO of Faraday Technology. “As a leading provider of ASIC design service and IP solutions, Faraday empowers customers to streamline their R&D efforts, accelerating time-to-market and enhancing business opportunity,” he added.