HSINCHU, TAIWAN-- January 21, 2021 -- Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, today unveiled its complete imaging and display high-speed interface IP set on UMC’s 40LP and 28HPC/HPC+ process nodes, including MIPI D-PHY (TX/RX, controller), V-by-One HS (TX/RX, controller), and LVDS (TX/RX, I/O). These IPs are designed with optimized PPA (power, performance, area) for various imaging and display systems, such as 4K/8K projectors, pico projectors, automotive HUDs, in-vehicle infotainment systems, POS systems, AR/VR devices, wearable devices, robots, multifunction printers (MFP), digital cameras, and surveillance cameras.

Faraday provides application-oriented design services for MIPI D-PHY, such as multiple-TX-lane IP solutions for high-resolution and high-frame-rate display engines, rich RX combo IO solutions (MIPI/sub-LVDS/HiSPi/CMOS) to shrink chip size, and flexible data/clock lane configurations to support various device interfaces. In addition, Faraday offers its MIPI combo PHY evaluation board to help customers create prototypes for system-level development and verification at the pre-silicon stage to ensure design qualities.

“Our comprehensive imaging and display interface IP solutions have successively been adopted for state-of-the-art applications at UMC 28nm and 40nm nodes,” said Flash Lin, chief operating officer of Faraday. “By combining our proven records of imaging and display ASIC design experience, we can help our customers develop more high-performance systems with high-quality benefits to address the growing demand for imaging and display applications.”